//--------------------------------------------------------------------------
//
// $Id$
//
// Module Name:         testbed.v
//
// Created:             June 24, 1998
//
// Author:              verilog@usa.net
//
// Notes:		This Verilog inter-connect file generated 
//			automatically by MKTREE
//
//			Click on "memory" to see that file or
//			Click here to return to "memory.tree"
//
//--------------------------------------------------------------------------

//--------------------------------------------------------------------------
// This file generated by MKTREE (Ver. 3.910).
// E-mail verilog@usa.net for support/information.
//--------------------------------------------------------------------------

module testbed;
    wire	[31:0]	data_bus;
    wire	[3:0]	ocs;
    wire	[11:0]	addr;

    host host
		(
		 .data_bus(data_bus),
		 .ocs(ocs),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .clk(clk)
		); // host

    memory memory
		(
		 .data_bus(data_bus),
		 .ocs(ocs),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .clk(clk)
		); // memory


endmodule // testbed