//--------------------------------------------------------------------------
//
// $Id$
//
// Module Name:         memory.v
//
// Created:             June 24, 1998
//
// Author:              verilog@usa.net
//
// Notes:		This Verilog inter-connect file generated 
//			automatically by MKTREE
//
//			Click on "memory_bank" to see that file,
//			Click here to return to "testbed.v"
//			Click here to return to "memory.tree"
//
//--------------------------------------------------------------------------

//--------------------------------------------------------------------------
// This file generated by MKTREE (Ver. 3.910).
// E-mail verilog@usa.net for support/information.
//--------------------------------------------------------------------------

module memory (data_bus, ocs, we_, oe_, addr, clk);

    inout	[31:0]	data_bus;
    input	[3:0]	ocs;
    input		we_;
    input		oe_;
    input	[11:0]	addr;
    input		clk;

    memory_bank even_bank
		(
		 .ce1_(1'b0),
		 .data_bus(data_bus),
		 .ocs(ocs),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .clk(clk)
		); // even_bank

    memory_bank odd_bank
		(
		 .ce1_(1'b1),
		 .data_bus(data_bus),
		 .ocs(ocs),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .clk(clk)
		); // odd_bank


endmodule // memory