//--------------------------------------------------------------------------
//
// $Id$
//
// Module Name:         memory_bank.v
//
// Created:             June 24, 1998
//
// Author:              verilog@usa.net
//
// Notes:		This Verilog inter-connect file generated 
//			automatically by MKTREE
//
//			Click here to return to "memory.v"
//			Click here to return to "testbed.v"
//			Click here to return to "memory.tree"
//
//--------------------------------------------------------------------------

//--------------------------------------------------------------------------
// This file generated by MKTREE (Ver. 3.910).
// E-mail verilog@usa.net for support/information.
//--------------------------------------------------------------------------

module memory_bank (ce1_, data_bus, ocs, we_, oe_, addr, clk);

    input		ce1_;
    inout	[31:0]	data_bus;
    input	[3:0]	ocs;
    input		we_;
    input		oe_;
    input	[11:0]	addr;
    input		clk;

    mem mem0
		(
		 .data(data_bus[7:0]),
		 .ce2(ocs[0]),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .ce1_(ce1_),
		 .clk(clk)
		); // mem0

    mem mem1
		(
		 .data(data_bus[15:8]),
		 .ce2(ocs[1]),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .ce1_(ce1_),
		 .clk(clk)
		); // mem1

    mem mem2
		(
		 .data(data_bus[23:16]),
		 .ce2(ocs[2]),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .ce1_(ce1_),
		 .clk(clk)
		); // mem2

    mem mem3
		(
		 .data(data_bus[31:24]),
		 .ce2(ocs[3]),
		 .we_(we_),
		 .oe_(oe_),
		 .addr(addr),
		 .ce1_(ce1_),
		 .clk(clk)
		); // mem3


endmodule